This paper presents an implementation of a 3-bit soft decision Viterbi decoder. It uses survivor path with parameters for wireless communication in an attempt to reduce the power, area, and cost. At the same time, it increases the speed. The circuit design supports a constraint length of seven and a code rate of 0.5. The convolution encoder and the 3-bit soft decision Viterbi decoder are implemented on Virtex-6 XC6VLX240T FPGA at 66 MHZ core frequency starter kit. Xilinx ISE12.1 series is used for simulation. The implemented design shows an area overhead reduction of 50% compared to Spartan 3E device. In a Virtex-6 the proposal achieved 2014 LUTs in compared with Spartan 3E solutions, 3155 LUTs are achievable compared with Virtex_5 solutions. In addition, Slice Registers occupied 1011 , while 3214 in Spartan 3E then 69% are achievable in Virtex 5, then Virtex 6 better than previous state-of the- art solutions in terms of area, Higher data rates. Moreover, the implemented Viterbi decoder tested against an additive white Gaussian noise channel (AWGN) and consequently has gained more popularity in many applications.